Digital communication receivers sample an incoming waveform and then reliably detect the sampled data. Typically, a receiver includes a Clock and Data Recovery (CDR) system to recover the clock and data from an incoming data stream. The CDR system generates a clock signal having the same frequency and phase as the incoming signal, which is then used to sample the received signal and detect the transmitted data.
CDR systems often employ well-known multiple stage proportional-integral (PT) digital loop filters, typically having multiple integrators in series. In a second order filter, for example, the first integrator includes a proportional register (PREG), and the second integrator includes an integral register (IREG), in a known manner. The CDR system recovers or locks to an initially unknown phase offset and frequency offset present in the incoming signal. The integral state of the loop is directly related to the frequency offset. The integral register is typically initialized to a value of zero (0) and the integral register value will eventually converge to a value that is proportional to the frequency offset.
While existing CDR systems perform well for a reasonable chip area and power budget, a need exists for techniques to enhance the performance of such CDR systems. A further need exists for techniques for monitoring the quality of the performance of the CDR system for staying locked to the correct frequency.